I've gone back to the data books many times and with few exceptions, find HC to be just slightly faster than LS. Of course if the propagation delays become an issue as mentioned above, 74AC (advanced CMOS) is quite a bit faster. Take for example the 74xx00 quad NAND gate. My National Semiconductor data books put the 00's maximum/typical propagation delays at 16/10ns for LS, 16/8 for HC, and 6.5/4.5 for AC, H→L, 25°C, 50pF load. For the '138 3-to-8-line decoder, it's 42/28 for LS, 36/18 for HC, and 9.0/6.0 for AC, A(n) to O(n), H→L, 25°C, 50pF load. Since the specs are not always made with the same capacitance load, it becomes a little hard to compare apples to apples and I had to interpolate from the supplied data on a few numbers. Still, the error here will be under 5%. As you can see, HC is faster (ie, takes less propagation time) than LS in these cases (as in most, but not all).
You might be able to get away with designing one-of-a-kind home projects using the typical propagation delays, but you definitely cannot when you're designing something that will get marketed. Suppose you want your home-made 65c02 computer to run at 5MHz (5 times as fast as your Commodore 64, but still not nearly as fast as what can be done today with a 65c02). That means a clock cycle is 200ns. Since a RAM read or write takes place in half a cycle, that means you have 100ns, if you are using one of the very simple circuits already shown in the address-decoding section. Now suppose the data sheet for your particular make and speed of 65c02 says the data you're reading from the RAM has to be stable at the processor's pins at least 20ns before Φ2 goes down to be latched in reliably. That takes the available time down to 80ns. Now suppose you have 70ns memory. Now you're down to 10ns. The address lines on the RAM as well as the R/W line must be valid and stable before Φ2 goes up, and then you have a maximum of 10ns after that to make sure the RAM gets enabled. You can see that the 74LS and 74HC parts mentioned above are definitely out, unless you get faster memory. The 74AC logic might do the job, depending on your glue logic scheme.
This is a little oversimplified; but what I'm getting at here is that the propagation delays are not just something you can ignore, except sometimes at clock speeds that are so low that virtually any logic family and memory will be fast enough. 1MHz will usually qualify, although I still wouldn't recommend using 74C- or 4000-series logic for this application. You can see that you'll need faster memory if you want to be able to count on operation above 5MHz. SRAM is available in DIPs down to 15ns, and sometimes 12. Going that fast will require extra care in the construction of your computer board, although it can still be done with wire-wrap if you do it right. More on that later.
I must point out Jeff Laughton's excellent animated, drawn-to-scale (unlike most in data sheets), visualizations of timing margins, in the forum topic "Timing Diagrams. Visualizing 65xx Timing." These .gif files help understand what timings are constant and what varies with clock speed-- info that's very helpful when selecting and planning your glue logic.
True, we went by the worst-case timing specifications above (but only at 25°C and not at the temperature extremes), and it's highly unlikely that every part involved will be pushing the max. But if you want to be sure before you build it that it will work at a certain speed, you have to design around these worst-case specifications. If you're just building a single piece for yourself, then after it's made you can turn up the clock speed and see how much you can get away with. (See how at the end of the Clock Generation section.) My workbench computer has a 6MHz processor, 4MHz peripheral ICs, 55ns SRAM, and 70ns EPROM. Since it will always be used near room temperature, I just ran the clock speed up while it was sitting on the work bench, and found that it started having trouble when it got over 7MHz. So I backed down a bit to have some margin and plugged in a crystal oscillator to run it at 5MHz.
Back to logic families. If you're hesitant about the CMOS logic because you know it can be damaged by amounts of static too
small to feel, you're not alone. However, consider that the microprocessor, memories, and I/O ICs have static-sensitive
MOS inputs as well (even if they're NMOS and not CMOS), and that these parts do all have protection diodes from each input to ground
and Vdd built in. These diodes turn on if the input voltage goes more than a fraction of a volt below the chip's ground or above
the its Vdd line. To hold the input capacitance down, these diodes are very tiny and cannot handle much current; so the bigger
static discharges can still damage the part. Most manufacturers' specs say the input diodes will handle 20mA, but a good zap will
far exceed that amount. By the way, bipolar transistors can be damaged by static too, but they can handle a lot more. The
reverse-voltage breakdown of a PN junction does not damage it as long as the current is within certain limits. In fact, production
testing done on 100% of bipolar transistors is to put a small current (around a couple of mA) through the B-E and C-B junctions
backwards, and see if the voltages are high enough to qualify for sale as a certain part number. These voltages are often in the
neighborhood of 5-10V for B-E and 30-60V for C-B. It's very unlikely that your body static will damage ICs that only have bipolar
transistors or JFETs but no MOS. (But see the "Static-Handling Precautions" section below and you'll do fine.)
Do I Need Bus Transceivers?
First, what are bus transceivers? These are ICs like the 74HCT245 that go between the processor and the things out on its buses, there to give more strength to drive the buses. Vintage home computers had these back in the days of NMOS 6502's with weak output drivers and of small memories that required lots of ICs to get much total memory. Bus-transceiver ICs usually have 8 bits each, so an 8-bit data bus and 16-bit address bus would require three of these ICs. The one for the data bus needs to be directional, with the direction at any given moment being determined by the DIR pin which gets connected to the R/W line.
You will not need bus transceivers with a CMOS 6502, especially WDC's current production. I have done some brief tests on the W65C816S's pin drivers. Their behavior was pretty much symmetrical, able to pull up just as
hard as they can pull down, unlike TTL which cannot pull up as hard as down. If you had to boil my test results down to
approximations and treat the circuits as just a resistance, the data pin drivers acted very roughly like a SPDT switch with 50Ω in
series with the common terminal (ie, the output); and the address bus pins, as a SPDT switch with 60Ω in series. I have not had
the chance to test a W65C02S; but I suspect WDC used the same circuits on the '02 and the '816, which would make it much
stronger than the data sheet says. The time constant of 60Ω times the capacitive load of 10 CMOS loads is around 3ns, which is
less added delay than you'll get from a bus transceiver IC. Daryl Rictor had no
trouble running my 4Mx8 5V 10ns SRAM module on his SBC-4 single-board
computer at 12MHz with a barefoot '816 (ie, no bus trasceivers), driving this module and three daughter boards at the same time. The
module has 8 bussed SRAM ICs.
So how do you avoid damaging these NMOS or CMOS parts? If you look at commercial assembly plants, distributors, or manufacturers, you'll see they've gone to amazing lengths to get rid of all static-- the special static-dissipative floor tiles, shoe covers, smocks, wrist bands, anti-static mats, grounded tools, air ionizers and humidifiers, etc.. As long as you remain constantly aware of what causes static damage, you can get away with nothing more than an anti-static workbench mat. I have a friend who works on this stuff without even the mat, but I don't recommend it. Too much care is required.
You can get a static-dissipative mat from Jameco for as little as $9. I would recommend going with a bigger one at $26. I personally use two, side by side. If you're a bit absent-minded, maybe you better get the wrist strap too. These come with a ground wire typically with a clip to connect to a post on your oscilloscope or other workbench equipment that is grounded. The resistance of the mat or the wrist strap cord is so high that you won't feel anything if you touch the AC power line and complete a circuit to ground through the wrist strap or the mat, but it will still discharge the static build-up in your body.
Keep your work on the mat. If you don't use the wrist strap, make sure that when you come to the workbench, you don't touch any static-sensitive parts until either you have touched something like a grounded post or metal case of your workbench test equipment, or had your hands or arms leaning on the anti-static mat for five or ten seconds. I usually work in short sleeves, and keep at least one forearm in constant contact with the static-dissipative mat. That avoids static build-up that could otherwise occur from something as simple as slight movement in the chair or moving my feet around on the floor. Handling boards and MOS ICs this way, I've never caused damage with static. I'm not in an arid environment though like you might be if you live in the desert. If you are in such a dry environment, do use a humidifier.
Without being grounded, you can still pick up a breadboard without damaging the MOS parts on it if the first part you touch (other
than insulating materials) is a pin, screw, foil, LCD frame, or other conductor that goes to the board's ground (Vss). If the
first thing you touch on the breadboard is something like a data bus line, you're more likely to cause damage.
For further reading
There can sometimes be problems if you try to drive CMOS inputs (without the "T", like 74HC instead of 74HCT) with LSTTL outputs, as the latter may not pull up high enough to produce a valid logic "1" at the CMOS inputs. I generally push for all CMOS (which would avoid the problem, with or without the "T"), but sometimes people in other countries where parts availability is poor have their reasons for using LS. The following .pdf Fairchild applications notes (and two non-Fairchild pages) help understand the differences and how to interface the different families: