NMOS-CMOS 6502 differences

hardware differences
software differences (and a combination hardware/software difference)
availability
for further reading

On certain forums, and in a recent web search, I have found that some 6502 enthusiasts are apparently still unaware of the CMOS 6502 (65c02) which was out in the early 1980's and of the benefits it offers over the original NMOS 6502. On one forum, someone said something about the BRA (Branch Relative Always) instruction, and another said, "The 6502 doesn't have a BRA instruction, but I think I know what you mean," thinking the first one was confusing it with a different processor. I've seen enthusiasts' web pages saying the 6502 was offered in 1MHz and 2MHz versions, the writers being unaware that all the them being made since the mid-1990's are guaranteed to meet the timing specifications at 14MHz or better, and that the fastest ones are put at the heart of custom ICs and are running over 200MHz.

Hardware differences

CMOS allows much higher speeds. All the 65c02's being made today are guaranteed to meet specs at at least 14MHz. All WDC ones are tested at 20MHz. 6502.org forum member "plasmo" got both a W65C02S and a W65C816S to run at 36MHz, 40MHz at 5.3V (see here). Also, forum member "Windfall" got both running at 24MHz at 3.3V, three times the speed guaranteed for that voltage by the data sheet! (See here.)
CMOS can run at lower voltages. The WDC W65C02S is spec'ed from 1.71V to 5.25V.
CMOS requires less power, and if all loads are CMOS also, power is proportional to frequency, dropping to essentially zero when the clock is stopped.
CMOS allows the clock to be stretched or stopped indefinitely without losing data. WDC's allows stopping the clock in either phase. Other brands of 65c02 could only stop when Φ2 was high. NMOS was not guaranteed to run reliably below 50 or 100kHz depending on brand.
CMOS allows a crystal to be hung directly on Φ0 & Φ1 for oscillation, or an RC hung directly on these plus Φ2, eliminating the need for an external oscillator for some applications. (See the clock-generation page of the 6502 primer on this site.) NMOS always needed the external oscillator. (Most recently however, WDC has said they no longer test the timings of these three relative to each other, and they prefer that you use an external oscillator, even though all the circuitry is still there, operational, for using it as an onboard oscillator. In critical cases, a separate oscillator may still be preferable.)
CMOS can pull all the way up to VDD. Output high voltage with light load may be only a few mV from VDD.
CMOS offers better noise immunity.
CMOS: Some manufacturers put weak pull-ups to VDD on IRQ, NMI, RDY, RST, SO, and on WDC's, BE (bus enable). (Since not all did, you will need to check the data sheet before leaving them unconnected.)
CMOS (WDC W65C02S and others' 65C102 and 65C112) has more signals, for a wider range of hardware applications: bus enable (BE, DIP pin 36, PLCC pin 40, and PQFP pin 34), and memory lock (ML, DIP pin 5, PLCC pin 6, and PQFP pin 44), and on the WDC part, vector pull (VP, DIP pin 1, PLCC pin 2, and PQFP pin 40). Note that pin 1 of NMOS and most non-WDC CMOS µP's in the 40-pin DIP is ground (like pin 21); so if you want to make a board able to take all brands, it would be good to have pin 1's function jumper-selectable.
CMOS is available in 44-pin PLCC and PQFP, not just 40-pin DIP. At the time of this writing (July 2015), the PQFP is only available from WDC, not their distributors. The PQFP definitely saves a lot of board space.
CMOS has stronger bus-drive capability, far stronger than the datasheets let on. I have done some brief tests on WDC's W65C816S's pin drivers which I suspect are the same ones used they used on the W65C02S. Their behavior was pretty much symmetrical, able to pull up just as hard as they can pull down, unlike TTL which cannot pull up as hard as down. If you had to boil my test results down to approximations and treat the circuits as just a resistance, the data pin drivers acted very roughly like a SPDT switch with 50Ω in series with the common terminal (ie, the output); and the address bus pins, as a SPDT switch with 60Ω in series. The time constant of 60Ω times the capacitive load of 10 CMOS loads is around 3ns, which is less added delay than you'll get from a bus transceiver IC.
In a separate test on WDC's W65C22S VIA (not the W65C22N) I/O pins years earlier, I found they were each able to pull to within 0.8V of either rail with a 220-ohm resistor to the opposite rail, meaning a 19mA load, even pulling up, and give 50mA into a dead short. Rockwell's R65C22 could pull down with 100mA into a dead short, but could not pull up as hard, not being symmetrical like WDC's.
WDC's CMOS parts, with the exception of the 65c22N and 65c51N, have CMOS input levels, and feeding these inputs with 74LS logic (which there's no reason to use anyway) is not guaranteed to work, since 74LS cannot pull up nearly as high as CMOS outputs can.
According to the NMOS data sheets (we wonder if this may be an error in them), the RDY input timing may vary between manufacturers regarding which Φ2 edge it is referenced to. Some reference it to Φ2's rising edge, and others to its falling edge. Rockwell even puts it after the rising edge which definitely looks like a mistake. All the CMOS data sheets give it as a setup time before the fall of Φ2.
Related, but regarding the WDC's VIA, the W65C22S (but not the W65C22N) commonly used with the 65C02:
- Its I/O pins, in the input mode, are true CMOS inputs. The heavy LS-type load presented by other VIAs' (even CMOS ones') I/O pins in input mode was a problem for some applications.
- It has bus-holding devices on the I/O pins which keep the input at the last-driven logic level. If you drive it high or low, then disconnect the drive, it will hold itself at that level. There is no problem with leaving unused pins unconnected like there is with many other CMOS inputs.
- It has a totem-pole IRQ output rather than the open-drain output that others have. This is addressed in the interrupts primer. It may seem like an undesirable feature since you can no longer wire-OR the IRQ pins together but must use an AND gate instead; but the IRQ output was made this way so the rise time of the IRQ input to the µP would not be limited by the bus capacitance and the pull-up resistor causing it to float up too slowly for some situations when operating at maximum clock speeds (up to 25MHz).

Software differences

CMOS has more instructions and addressing modes.

CMOS 65c02 new instructions that were not on the NMOS 6502 at all:

instruction    op code
& addr mode    (in hex)    description

BRA rel          80       Branch Relative Always (unconditionally), range -128 to +127.

PHX              DA       PusH X.  ‾⌉
PLX              FA       PulL X.   |  No need to go through A for these anymore.
PHY              5A       PusH Y.   |
PLY              7A       PulL Y.  _⌋

STZ  addr        9C       ‾⌉
STZ  addr,X      9E        |  STore a Zero, regardless of what's in A, X, or Y.
STZ  ZP          64        |  Processor registers are not affected by STZ.
STZ  ZP,X        74       _⌋

TRB  addr        1C       ‾⌉  Test & Reset memory Bits with A.
TRB  ZP          14       _⌋

TSB  addr        0C       ‾⌉  Test & Set memory Bits with A.
TSB  ZP          04       _⌋

BBR  ZP       0F-7F [1]   Branch if specified Bit is Reset. ‾⌉ These are most useful
BBS  ZP       8F-FF [1]   Branch if specified Bit is Set.    | when I/O is in ZP.  They
RMB  ZP       07-77 [1]   Reset specified Memory Bit.        | are on WDC & Rockwell but
SMB  ZP       87-F7 [1]   Set specified Memory Bit.         _⌋ not GTE/CMD or Synertek.

STP              DB       SToP the processor until the next RST.     ‾⌉
                          Power-supply current drops to nearly zero.  |  These two are
                                                                      |  on WDC only.
WAI              CB       WAIt.  It's like STP, but any interrupt     | 
                          will make it resume execution.  Especially  |
                          useful for superfast interrupt response,    |
                          with zero latency.  See interrupts primer. _⌋


Note: [1] Only the most-significant digit of the op code changes; so for example BBR's
op codes are 0F, 1F, 2F, 3F, 4F, 5F, 6F, and 7F, for BBR0 to BBR7.  The bit number is
specified in the op code rather than the operand.  These operate in ZP only.  Rockwell
added these first, for their microcontrollers that had I/O in ZP.  WDC added them in
the early 1990's.  The Aug '92 data sheet shows the W65C02S available without them, and
the W65C02SB with them, but said eventually they would all have them, and be labeled
W65C02S, without the B.  By the July '96 data sheet, these instructions were standard
in all of them.

CMOS 65c02 instructions' addressing modes that were not on the NMOS 6502:

instruction    op code
& addr mode    (in hex)    description

ADC  (addr)      72       ADC absolute indirect
AND  (addr)      32       AND absolute indirect
BIT  addr,X      3C       BIT absolute indexed
BIT  ZP,X        34       BIT zero-page indexed
BIT  #           89       BIT immediate
CMP  (addr)      D2       CMP absolute indirect
DEC  A           3A       DECrement accumulator (alternate mnemonic: DEA)
INC  A           1A       INCrement accumulator (alternate mnemonic: INA)
EOR  (addr)      52       EOR absolute indirect
JMP  (addr,X)    7C       JMP absolute indexed indirect
LDA  (addr)      B2       LDA absolute indirect
ORA  (addr)      12       ORA absolute indirect
SBC  (addr)      F2       SBC absolute indirect
STA  (addr)      92       STA absolute indirect

Appetite whetter: the 65816 adds even more instructions and addressing modes, filling out the table, and is able (but not required) to handle 16 bits of data at a time, as well as 24-bit addresses, and has a 16-bit stack pointer and more stack-addressing modes, relocatable zero page (so for example each task can have its own), and other attractions. It is actually easier to program than the '02 is if you're constantly handling 16-bit data, and is much better suited for relocatable code, multitasking, etc.. If it seems scary, keep in mind that all the new '816 features can be used or ignored at one's leisure, and picked up little by little as you're ready. You can start out by initially using it just like a 6502.

On the NMOS 6502, the "illegal" op codes (see this page for more explanation), performed strange operations, undocumented by manufacturers, and were popular, and were used in the GEOS GUI for the Commodore 64, to meet the speed and memory requirements to make GEOS a viable software product on that limited machine. The CMOS 6502 does not have those, but its new instructions and addressing modes are more useful anyway. CMOS still leaves some op codes unused, but they do not crash the µP like some of the illegal op codes do on NMOS.
On the CMOS 65c02, illegal op codes initially act as NOPs, but can be useful for single-cycle time delays, and more interestingly, for effectively extending the processor's instruction set; for example, Jeff Laughton's fast (1-cycle) 65c02 I/O methods using the illegal op codes in the _3 and _B columns, his KimKlone 65c02 w/ pointer-arithmetic-friendly extended address space and 9-cycle ITC Forth NEXT instruction, and the memory-mapping ops of the Hudson 65c02-based processor used in the TurboGrafx-16 Entertainment SuperSystem. In this respect, these could be considered to be combination hardware/software differences.
This table shows the number of bytes and cycles taken by the CMOS instructions:

It's from the forum topic Introducing Tali Forth for the 65c02 (ALPHA)". Note the software ability to skip over two bytes. You can do for example:
```
              .DB  $DC    ; This is the illegal op code of a 3-byte, 4-cycle NOP.
branch_dest:  LDA  #71    ; Its operand will be this 2-byte, 2-cycle instruction.
              <continue>
```
If you branch or jump to branch_dest, the LDA #71 will be executed; but if you arrive there without branching, ie, from directly above it, the LDA will get skipped, and there will be no effect on status bits. Actually, the LDA #71 will get loaded as a two-byte operand for the illegal $DC instruction, and the address that operand points to will get read and the data discarded, like an absolute load-and-discard instruction; so you might need to be careful that you don't read an I/O register where the I/O IC's status would be changed by doing so (like the situation with BIT addr). The danger of doing it inadvertently will be very low.
CMOS corrects all the bugs and quirks of the NMOS:
- JMP(xxFF): NMOS did not increment the page when reading the second byte, so the jump was wrong.
- N, V, and Z flags were incorrect after decimal operation (but C was ok). (CMOS adds one cycle to fix them.)
- A BRK instruction that was being fetched when an interrupt hit was ignored on NMOS. (CMOS executes the BRK, then takes the interrupt.)
- D was not cleared on RST, IRQ, or NMI. (CMOS does clear D in these situations.)
- RDY being negated (pulled low, as RDY is positive logic) during write cycle had no effect. (CMOS gives the expected wait state(s).)
- Indexing across a page boundary caused an extra read of an invalid address, which could cause trouble in some hardware. (CMOS does an extra read of the last instruction byte instead.)
- RMW instructions at effective address did one read and two writes, which could cause trouble if it's I/O. (CMOS does two reads and one write.)

Availability

None of the NMOS parts have been made in many years (decades?) but NOS (new old stock) can sometimes be found, and some distributors like Jameco have "pulls," ie, ones that have been pulled out of circuit boards, mostly used. Some of the CMOS parts are also discontinued, the ones that come to mind being the GTE/CMD 65C03, '04, '05, '06, 07, '12, '13, '14, '15, '102, '103, '104, '105, '106, '107, '112, '115, '150, and '151, the Rockwell '19, and the WDC 65C802. WDC plans to continue making the CMOS 65C02, '816, '134 µC, '265 µC, and I/O ICs indefinitely, at least in DIP and PLCC and some also in PQFP, and there are many distributors selling them. We try to keep the forum sticky topic "65xx parts sources" up to date, so please refer there.

For further reading

65c02 advantages (forum topic)
A taken branch delays interrupt handling by one instruction (forum topic) There seems to be a difference between NMOS and CMOS in this area as well.
A 65C02 bug? (it was a bug in the documentation, not the processor) (forum topic) See Jeff's post on cycle timing differences between NMOS & CMOS in R-M-W instructions.
Least Obvious Incompatibility (forum topic)
65c02 data sheet (.pdf) from WDC
65816 data sheet (.pdf) from WDC
"Programming the 65816-Including the 6502, 65C02 and 65802," the outstanding programming manual by David Eyes and Ron Liechty. By far the best.
I came across this CPU World page in Feb 2018 giving more details on the variants like 6504, 6505, 6506, 6507, etc. (not so much the NMOS-CMOS differences).

links from my links page, under "65-family processors", at http://wilsonminesco.com/links.html#65fam :
6502 origins
65816 origins, 6516, 65032, 65832
65CE02 improvements over the 65c02
6516 (Synertek) 16-bit pseudo-6502 for Atari 400/800 computers, never made it to market
65020 double-wide 6502 proposal
HuC6280, a PC Engine using a special version of the 65c02 (with all the modern CMOS instructions minus STP and WAI), with a memory management unit (MMU). Of special interest are the instructions directly involved with memory mapping and moving, and a T flag, which when set (using SET), causes the accumulator instructions AND, EOR, OR, and ADC to operate on the ZP address pointed to by X instead, without affecting A. In a way, it makes it like having 257 accumulators, for those instructions.
6502EX (6502 extended to 32 bits)
65Org32 developments of ideas for an all-32-bit 65816 extension (forum topic)

If you know of additional differences I should add, or see errors, please email me.

last updated May 6, 2024 Garth Wilson email wilsonminesBdslextremeBcom (replacing the B's with @ and .)