On certain forums, and in a recent web search, I have found that some 6502 enthusiasts are apparently still unaware of the CMOS 6502 (65c02) which was out in the early 1980's and of the benefits it offers over the original NMOS 6502. On one forum, someone said something about the BRA (Branch Relative Always) instruction, and another said, "The 6502 doesn't have a BRA instruction, but I think I know what you mean," thinking the first one was confusing it with a different processor. I've seen enthusiasts' web pages saying the 6502 was offered in 1MHz and 2MHz versions, the writers being unaware that all the them being made since the mid-1990's are guaranteed to meet the timing specifications at 14MHz or better, and that the fastest ones are put at the heart of custom ICs and are running over 200MHz.
In a separate test on WDC's W65C22S VIA (not the W65C22N) I/O pins years earlier, I found they were each able to pull to within 0.8V of either rail with a 220-ohm resistor to the opposite rail, meaning a 19mA load, even pulling up, and give 50mA into a dead short. Rockwell's R65C22 could pull down with 100mA into a dead short, but could not pull up as hard, not being symmetrical like WDC's.
CMOS 65c02 new instructions that were not on the NMOS 6502 at all:
instruction op code
& addr mode (in hex) description
BRA rel 80 Branch Relative Always (unconditionally), range -128 to +127.
PHX DA PusH X. ‾⌉
PLX FA PulL X. | No need to go through A for these anymore.
PHY 5A PusH Y. |
PLY 7A PulL Y. _⌋
STZ addr 9C ‾⌉
STZ addr,X 9E | STore a Zero, regardless of what's in A, X, or Y.
STZ ZP 64 | Processor registers are not affected by STZ.
STZ ZP,X 74 _⌋
TRB addr 1C ‾⌉ Test & Reset memory Bits with A.
TRB ZP 14 _⌋
TSB addr 0C ‾⌉ Test & Set memory Bits with A.
TSB ZP 04 _⌋
BBR ZP 0F-7F  Branch if specified Bit is Reset. ‾⌉ These are most useful
BBS ZP 8F-FF  Branch if specified Bit is Set. | when I/O is in ZP. They
RMB ZP 07-77  Reset specified Memory Bit. | are on WDC & Rockwell but
SMB ZP 87-F7  Set specified Memory Bit. _⌋ not GTE/CMD or Synertek.
STP DB SToP the processor until the next RST. ‾⌉
Power-supply current drops to nearly zero. | These two are
| on WDC only.
WAI CB WAIt. It's like STP, but any interrupt |
will make it resume execution. Especially |
useful for superfast interrupt response, |
with zero latency. See interrupts primer. _⌋
Note:  Only the most-significant digit of the op code changes; so for example BBR's
op codes are 0F, 1F, 2F, 3F, 4F, 5F, 6F, and 7F, for BBR0 to BBR7. The bit number is
specified in the op code rather than the operand. These operate in ZP only. Rockwell
added these first, for their microcontrollers that had I/O in ZP. WDC added them in
the early 1990's. The Aug '92 data sheet shows the W65C02S available without them, and
the W65C02SB with them, but said eventually they would all have them, and be labeled
W65C02S, without the B. By the July '96 data sheet, these instructions were standard
in all of them.
CMOS 65c02 instructions' addressing modes that were not on the NMOS 6502:
instruction op code
& addr mode (in hex) description
ADC (addr) 72 ADC absolute indirect
AND (addr) 32 AND absolute indirect
BIT addr,X 3C BIT absolute indexed
BIT ZP,X 34 BIT zero-page indexed
BIT # 89 BIT immediate
CMP (addr) D2 CMP absolute indirect
DEC A 3A DECrement accumulator (alternate mnemonic: DEA)
INC A 1A INCrement accumulator (alternate mnemonic: INA)
EOR (addr) 52 EOR absolute indirect
JMP (addr,X) 7C JMP absolute indexed indirect
LDA (addr) B2 LDA absolute indirect
ORA (addr) 12 ORA absolute indirect
SBC (addr) F2 SBC absolute indirect
STA (addr) 92 STA absolute indirect
Appetite whetter: the 65816 adds even more instructions and addressing modes, filling out the table, and is able (but not required) to handle
16 bits of data at a time, as well as 24-bit addresses, and has a 16-bit stack pointer and more stack-addressing modes, relocatable zero page (so for
example each task can have its own), and other attractions. It is actually easier to program than the '02 is if you're constantly
handling 16-bit data, and is much better suited for relocatable code, multitasking, etc.. If it seems scary, keep in mind that all the new '816
features can be used or ignored at one's leisure, and picked up little by little as you're ready. You can start out by initially using it just
like a 6502.
This table shows the number of bytes and cycles taken by the CMOS instructions:
It's from the forum topic Introducing Tali Forth for the 65c02 (ALPHA)". Note the software ability to skip over two bytes. You can do for example:
.DB $DC ; This is the illegal op code of a 3-byte, 4-cycle NOP. branch_dest: LDA #71 ; Its operand will be this 2-byte, 2-cycle instruction. <continue>If you branch or jump to branch_dest, the LDA #71 will be executed; but if you arrive there without branching, ie, from directly above it, the LDA will get skipped, and there will be no effect on status bits. Actually, the LDA #71 will get loaded as a two-byte operand for the illegal $DC instruction, and the address that operand points to will get read and the data discarded, like an absolute load-and-discard instruction; so you might need to be careful that you don't read an I/O register where the I/O IC's status would be changed by doing so (like the situation with BIT addr). The danger of doing it inadvertently will be very low.
None of the NMOS parts have been made in many years (decades?) but NOS (new old stock) can sometimes be found, and some distributors like Jameco have
"pulls," ie, ones that have been pulled out of circuit boards, mostly used. Some of the CMOS parts are also discontinued, the ones that come to
mind being the GTE/CMD 65C03, '04, '05, '06, 07, '12, '13, '14, '15, '102, '103, '104, '105, '106, '107, '112, '115, '150, and '151, the Rockwell '19,
and the WDC 65C802. WDC plans to continue making the CMOS 65C02, '816, '134 µC, '265 µC, and I/O ICs indefinitely, at least in
DIP and PLCC and some also in PQFP, and there are many distributors selling them. We try to keep the forum sticky topic
"65xx parts sources" up to date, so please refer there.
65c02 advantages (forum topic)
A taken branch delays interrupt handling by one instruction (forum topic) There seems to be a difference between NMOS and CMOS in this area as well.
A 65C02 bug? (it was a bug in the documentation, not the processor) (forum topic) See Jeff's post on cycle timing differences between NMOS & CMOS in R-M-W instructions.
Least Obvious Incompatibility (forum topic)
65c02 data sheet (.pdf) from WDC
65816 data sheet (.pdf) from WDC
"Programming the 65816-Including the 6502, 65C02 and 65802," the outstanding programming manual by David Eyes and Ron Liechty. By far the best.
I came across this CPU World page in Feb 2018 giving more details on the variants like 6504, 6505, 6506, 6507, etc. (not so much the NMOS-CMOS differences).
links from my links page, under "65-family processors", at http://wilsonminesco.com/links.html#65fam :
65816 origins, 6516, 65032, 65832
65CE02 improvements over the 65c02
6516 (Synertek) 16-bit pseudo-6502 for Atari 400/800 computers, never made it to market
65020 double-wide 6502 proposal
HuC6280, a PC Engine using a special version of the 65c02 (with all the modern CMOS instructions minus STP and WAI), with a memory management unit (MMU). Of special interest are the instructions directly involved with memory mapping and moving, and a T flag, which when set (using SET), causes accumulator instructions to operate on the ZP address pointed to by X instead, without affecting A! It makes it like having 257 accumulators.
6502EX (6502 extended to 32 bits)
65Org32 developments of ideas for an all-32-bit 65816 extension (forum topic)
If you know of additional differences I should add, or see errors, please email me.
last updated Feb 24, 2018 Garth Wilson email@example.com